The invention relates to the design of electronic circuit cards. Specifically, it is directed to electrically decoupling a BGA device with surface mount capacitors placed on the opposite side of the circuit card with respect to the BGA device and within the grid of vias and contacts used to route signal traces to the BGA device. This placement is motivated by the practice of placing decoupling capacitors as close as possible to the power and ground balls (pins) of the subject device for optimum electrical decoupling performance. Such placement is known in the art according to various techniques. However, each prior art technique has disadvantages relating to one or more of increased cost, reduced reliability, or increased constraints on the routing of signal traces within the BGA grid. The present invention therefore provides a new decoupling technique that mitigates the disadvantages of the prior art techniques discussed below.
Prior Art Solution No. 1
Referring to FIG. 1 and FIGS. 4A, 4B and 4C, LSI Logic has used shared vias on power and ground connections aligned in columns, in order to form a routing channel (i.e. a larger space between the row of shared vias and an adjacent row) through which connections can be routed. This is not a decoupling solution; however the assignee of this application has filed a patent application Ser. No. 10/761,343 in the USPTO on Jan. 22, 2004 entitled “Shared Via Decoupling for Area Arrays Components” on a solution that makes use of the shared via concept. FIG. 4 illustrates an example of this “shared-via” decoupling technique. The main drawback of the shared-via solution is that it is not always possible to share vias even though there are alternating power and ground rows. For example, in some cases the combined transient current of two power supply balls may exceed the limit for a via, in which case the two balls can not share a via, and consequently the shared-via decoupling technique for those balls can not be used.
Prior Art Solution No. 2.
Referring to FIGS. 2A and 2B, for 1.00 m pitch BGA components, one solution currently being used consists of plated through hole (PTH) used for via in pad (ViP) on the 0805 capacitor land pattern. The drawbacks of this solution are that the chip is required to have the power and ground balls configured in a very specific manner. The assumption in this case is that vias cannot be depopulated and that the capacitors must be connected as close as possible to the power and ground balls. FIG. 2 shows that in order for an 0805 capacitor to fit into the back side of a 1.00 mm grid, the power and ground balls that require decoupling need to be separated by either a signal or unused ball. In some applications this separation does not exist because of the pin-out of the BGA device, which may have been dictated by other constraints such as signal routing limitations, transient current limitations, etc.
Prior Art Solution No. 3
Referring to FIGS. 3A and 3B, another solution currently employed in recent designs, uses advanced printed wiring board (PWB) technology. This solution uses a combination of blind and sub-composite vias to allow access on the backside of the BGA component. In this case, component pitch, pin arrangement and capacitor size do not need to be specified and should work for many combinations. As a result, a “parking lot” like arrangement can be formed on the backside of a BGA component to maximize the number of decoupling capacitors that can fit into the available space. This option provides the highest degree of freedom for the design but results in higher board costs.
Prior Art Solution No. 4
Another technique is known as filled via. In this case, two adequately spaced apart through-hole (through board) vias are filled with conductive or non-conductive materials followed by a plating process so that each can act as a landing pad for an end of a surface mount decoupling capacitor. The capacitor is then electrically and mechanically connected to the circuit card by soldering it to the landing pads. A drawback to this technique is the possibility of a via becoming delaminated from the circuit card due to the differences in thermal expansion of the thin copper via, the materials used to fill the via, and the FR4 material used between copper layers of the circuit card. The process is considered to be high risk in the industry today with very limited sourcing. Additional to this reliability risk this technique is also adds about 30-40% to the cost of the circuit card.
In the order of the prior art discussed above, summarizing the main drawbacks of the above prior art solutions include the following:    1. The main drawback of the shared-via decoupling solution (Prior art No. 1) is that it can not be used in some applications, e.g. if transient currents are too high to share vias.    2. The main drawback of the plated through hole (PTH) Via in Pad (ViP) solution (Prior Art No. 2) is also that it is not applicable in some applications, e.g. when power, ground and signals balls (pins) cannot be arranged in the required pattern, i.e. power-signal-ground. Also, with that technique there is no test access for the signal pin under the decoupling capacitor and PTH ViP has caused some problems during x-ray inspection of circuit cards.    3. The main drawback to the “parking lot” solution (Prior Art No. 3), using High Density Interconnect (HDI) is the high cost of manufacturing the circuit card due to the blind and sub-composite vias used by the technique.    4. The drawbacks of the “filled via” solution (Prior Art No. 4) are the resulting increased reliability risk of filled vias becoming delaminated from the circuit card and the increased cost of the circuit card.